I received B-Tech degree from Haldia Institute of Technology, Haldia, West Bengal, India in 2004. I received M-Tech degree from Jadavpur University, Jadavpur, West Bengal, India in 2007. I received my PhD degree from NIT Durgapur, West Bengal, India in 2019. Since 2010, I am working as an assistant professor (III) in the department of Electrical Engineering, Dr. B. C. Roy Engineering College, Durgapur, West Bengal, India. In addition to that, photography and driving is my passion.
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PhD National Institute of Technology Durgapur - 2019 |
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M-tech Jadavpur University - 2007 |
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B-Tech Haldia Institute of Technology - 2004 |
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Higher Seondary Simlapal Madan Mohan High School - 2000 |
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Secondary Pukhuria High School - 1997 |
| Teaching | Research | Industry |
|---|---|---|
| 225 | 135 | 0 |
| Year | Title | Journal | DOI | Link |
|---|---|---|---|---|
| 24-02-2022 | Optimal design of second generation current conveyor using craziness-based particle swarm optimisation | International Jounal of Bio-Inspired Computation | DOI | View |
| 05-06-2017 | SEOA based optimal design of analogue CMOS amplifier circuits | International Journal of Bio-Inspired Computation | DOI | View |
| 10-02-2017 | Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization | International Journal of Machine Learning and Cybernetics | DOI | View |
| 03-07-2016 | CMOS analogue amplifier circuits optimization using hybrid backtracking search algorithm with differential evolution | Journal of Experimental & Theoretical Artificial Intelligence | DOI | View |
| 02-03-2016 | Optimal sizing and design of CMOS analogue amplifier circuits using craziness-based particle swarm optimization | International Journal of Numerical Modelling: Electronic Networks, Devices and Fields | DOI | View |
| Year | Title | Conference | DOI | Link |
|---|---|---|---|---|
| 2025 | A DVCC based Realization of Optimized Fractional Step Low Pass Filter | IEEE International Conference on Emerging Trends in Engineering and Medical Sciences | DOI | View |
| 2024 | Automated Design of CMOS-DACML Circuit | 2024 IEEE International Conference on Communication Computing and Signal Processing (ICCCS) | DOI | View |
| 2017 | Sizing of two stage Op-Amp using OHS algorithm | 2017 International Electrical Engineering Congress (iEECON) | DOI | View |
| 2017 | Optimal design of 5.5 GHz CMOS LNA using hybrid fitness based adaptive De with PSO | 2017 International Electrical Engineering Congress (iEECON) | DOI | View |
| 2016 | CMOS analog amplifier circuit sizing using opposition based harmony search algorithm | 2016 International Conference on Communication and Signal Processing (ICCSP) | DOI | View |
| SL. No. | Committee Name | Duration | Year |
|---|---|---|---|
| 1 | PCB AND CIRCUIT DESIGNING WORKSHOP 2025-26 | 03-02-2026 - 20-04-2026 | 2026 |
| 2 | INDUSTRY TALK #3 2025-26 MICROELECTRONICS | 06-09-2025 - 20-04-2026 | 2025 |
| 3 | EE INDUSTRY TALK #2 2025-26 ENERGY SUSTAINABILITY | 22-08-2025 - 20-04-2026 | 2025 |
| 4 | EE INDUSTRY TALK #1 2025-26 INDUSTRY 4.0 | 19-08-2025 - 20-04-2026 | 2025 |
| 5 | NAAC COMMITTEE 2025-26 | 01-07-2025 - 20-04-2026 | 2025 |